1. Field of the Invention
The present invention relates to a clamping divider having a clamping function applicable to image processors and multimedia information processors, an information processor having such a clamping divider, and a method of clamping in division.
2. Description of the Prior Art
Processing image data in real time is essential to multimedia technology and requires high-speed operations. The image data processing involves intensity calculations that involve clamping. The clamping is an operation to fix a result of an execution to a maximum or a minimum if the result is out of a range defined by the maximum and minimum.
A division execution of "a/b" is carried out according to, for example, Newton-Raphson algorithm. This algorithm employs the steps of:
A. multiplying the divisor b by some power of 2 to satisfy "1.ltoreq.b&lt;2" and retrieving a first approximate value X.sub.o of the reciprocal "1/b" of the divisor b from a table; PA1 B. repeating a calculation of "X.sub.l+1 =X.sub.l .multidot.(2-X.sub.l .multidot.b)" until a sufficiently accurate value X.sub.n is obtained; and PA1 C. calculating "a.multidot.X.sub.n ", and multiplying "a.multidot.X.sub.n " by reciprocal of the "some power of 2" employed in the step A.
The algorithm involving these steps is called "the algorithm Newton" in the following explanation.
When carrying out a division with the clamping, a prior art first calculates a quotient of the division. If the quotient is out of a range defined by predetermined maximum and minimum, the quotient is clamped to the maximum or minimum, to provide a final result of the division execution.
FIG. 1 shows a clamping divider according to a prior art. A division and the clamping carried out by the prior art according to the algorithm Newton will be explained based on pipeline cycles.
In a first cycle, a divisor is set in a register 50 and a dividend in a register 51.
In a second cycle, the divisor is standardized so that it is equal to or greater than 1 and below 2. Namely, the register 50 provides an output b1 to a priority encoder 60, which provides an encoded result b2 to a barrel shifter 61. The barrel shifter 61 also receives the output b1 of the register 50 and provides a shifted result b3 to a register 52.
In a third cycle, the register 52 provides an output b4 to a ROM 62, which provides an accessed value b5 to a register 53. The value b5 is an approximate value of the reciprocal of the divisor. The second and third cycles correspond to the step A of the algorithm Newton.
In a fourth cycle, a selector 70 receives an output b6 from the register 53 and an output b7 from a register 54 and selects the output b6 as a selector output b8. A selector 71 receives the output b4 from the register 52 and an output b9 from the register 51 and selects the output b4 as a selector output b10. A selector 72 receives a value b11 of "2" and a rounding value b12 and selects the rounding value b11 as a selector output b13. The selector outputs b8, b10, and b13 are supplied to a multiple accumulator (MAC) 63 having an adder/subtracter and a multiplier. The outputs b8 and b10 serve as multiplication terms and the output b13 as an addition term, so that the MAC 63 calculates "2-b8.times.b10" and provides an output b14 to the register 54.
In a fifth cycle, the selector 70 receives the outputs b6 and b7 of the registers 53 and 54 and selects the output b7 as the selector output b8. The selector 71 receives the outputs b4 and b9 of the registers 52 and 51 and selects the output b4 as the selector output b10. The selector 72 receives the values b11 and b12 and selects the value b12 as the selector output b13. The selector outputs b8, b10, and b13 are supplied to the MAC 63, which calculates "b8.times.b10," carries out a rounding process, and provides a result b14 to the register 54. The fourth and fifth cycles increase the accuracy of the reciprocal of the divisor obtained in the third cycle and correspond to the step B of the algorithm Newton.
A sixth cycle and following cycles repeat the operations of the fourth and fifth cycles until required accuracy is obtained on the reciprocal of the divisor.
If the required accuracy is obtained on the reciprocal of the divisor, the reciprocal of the divisor is multiplied by the dividend. Namely, the selector 70 selects the output b7 between the outputs b6 and b7 of the registers 53 and 54 and provides the selected one as the selector output b8. The selector 71 selects the output b9 between the outputs b4 and b9 of the registers 52 and 51 and provides the selected one as the selector output b10. The selector 72 selects the rounding value b12 between the values b11 and b12 and provides the selected one as the selector output b13. The selector outputs b8, b10, and b13 are supplied to the MAC 63, which provides a resultant output b14 to the register 54.
In the next cycle, the barrel shifter 64 receives the output b7 of the register 54 and the output b15 of the register 55 and shifts the output b7 in a direction opposite to the shifting direction of the second cycle by the same number of bits as in the second cycle, thereby providing a shifted output b16, i.e., a quotient. This corresponds to the step C of the algorithm Newton. Storing the output b2 of the priority encoder 60 in the register 55 may be finished before the cycle to operate the barrel shifter 64.
Thereafter, the output b16 of the barrel shifter 64 is supplied to a clamp judge circuit 65, which determines whether or not the quotient must be clamped and provides, as an output b17, one of the maximum clamp value, minimum clamp value, and quotient.
In this way, the clamping divider of the prior art of FIG. 1 must calculate a quotient before the clamping. Therefore, the prior art needs a long time to provide a final result, i.e., the output b17 of the circuit 65, to deteriorate a division calculating speed. In addition, the prior art must separately have the dedicated clamp judge circuit 65 to increase the size of the clamping divider.